There are at least three issues to be considered when designing an analog-to-digital converter (ADC): cost, accuracy and power consumption. For a monolithic silicon ADC the cost is primarily a function of the physical size of the converter. Smaller designs permit more devices to be processed using a given amount of resources, and the yields are typically higher since there is less overall area in which defects may be located. The higher yields in the manufacturing process further translate to lower cost.
The accuracy of an ADC is specified by the system in which it is to be used, and may be expressed in terms of a signal to noise ratio and overall resolution. Signal to noise describes the amount of desired signal present in the output compared to the undesired noise. This noise can distort the true signal and cause erroneous information to be output. As greater amounts of noise get included in the signal, the output becomes less accurate. Reduction of the noise component in the output of an ADC is a desirable design consideration.
Power consumption is another factor in the design of an ADC, particularly for portable or mobile devices which are battery powered. The less power used by portable or mobile devices the better since it extends the length of time the device may be operated before charging is required. Often however, reduced power consumption causes other parameters such as accuracy to degrade. Optimizing a design so that it consumes less power without losing accuracy is desirable.
One type of ADC is a Sigma-Delta ADC. During normal operation, a Sigma-Delta ADC with discrete-time sampling will sample an analog signal during a sample phase by storing a charge onto a capacitor. This charge is then integrated onto an integrator during an integration phase. Because the settling, or discharge, of discrete time signals, such as the sampled charge during integration, is an exponential RC decay, designing an operational amplifier capable of driving the peak current of the exponential decay (which is needed for only a brief instant) is wasteful. Therefore, operational amplifiers in discrete-time integrators have outputs which are sometimes limited relative to their input. As a result during peak current loads the output will not proportionately track the input. This skewing of the output gives power-efficient integration of discrete-time signals, but the result is a non-linear integration of continuous-time signals. A design which overcomes these limitations would be advantageous.